`include "defines.v"
module regfile(
	input wire clk,
	input wire rst,
	//写端口
	input wire[4:0] waddr,
	input wire[31:0] wdata,
	input wire we,
	//读端口1
	input wire[4:0] raddr1,
	input wire re1,
	output reg[31:0] rdata1,
	//读端口2
	input wire[4:0] raddr2,
	input wire re2,
	output reg[31:0] rdata2
);
	reg[31:0] regs[31:0];
	//读端口1
	always@(*) 
		if(rst == `RstEnable)
			rdata1 = `ZeroWord;
		else if(re1 == `ReadDisable || raddr1 == 0) 
			rdata1 = `ZeroWord;
		else if(raddr1 == waddr && we == `WriteEnable)
			rdata1 = wdata;
		else 
			rdata1 = regs[raddr1];
			
	//读端口2
	always@(*) 
		if(rst == `RstEnable)
			rdata2 = `ZeroWord;
		else if(re2 == `ReadDisable || raddr2 == 0) 
			rdata2 = `ZeroWord;
		else if(raddr2 == waddr && we == `WriteEnable)
			rdata2 = wdata;
		else 
			rdata2 = regs[raddr2];
			
	//写端口
	always@(posedge clk)
		if(rst == `RstDisable && waddr != 0 && we == `WriteEnable)
			regs[waddr] <= wdata;
endmodule